1. Field of the Invention
This invention generally relates to a semiconductor memory device, and, in particular, to a majority filter control of a delay lock loop.
2. Description of the Related Art
Modem integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of word lines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selection one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity may be divided into 64 sub-arrays, each having 256 K (218) memory cells.
Flash memory (sometimes called xe2x80x9cflash RAMxe2x80x9d) is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. Other types of memory may be erased and rewritten in smaller units, such as units at the byte level, which is more flexible, but slower than the block operations of flash memory. Flash memory is commonly used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written in block (rather than byte) sizes, making it faster to update. Applications employing flash memory include digital cellular phones, digital cameras, LAN switches, computers, digital set-up boxes, embedded controllers, and other devices.
Although forming the selected electrical connections may enable the circuits to perform their intended functions, undesirable electrical connections may result in a variety of malfunctions, e.g., short circuit paths may be established. Thus, semiconductor devices, such as the capacitors in memory cells, and conducting lines, such as the input/output lines, may generally be electrically isolated. For example, to ensure that devices, lines, and/or groups thereof, that form the semiconductor memory, are properly isolated, modem semiconductor processing involves the formation of shallow trench isolations (STI) in various regions of the substrate. These shallow trench isolations are typically formed by etching a trench in the semiconductor substrate and, thereafter, filling the trench with an isolation material, e.g., an insulator, such as silicon dioxide, silicon oxynitride, silicon nitride, or other like materials. However, it may be difficult to completely isolate the devices and/or lines. For example, defects in the semiconductor substrate or in the manufacturing process may form an undesirable conducting path between the devices and/or lines in the semiconductor memory that may cause the semiconductor memory to malfunction.
Typically, digital systems, such as memory systems, may comprise a delay lock loop that may be used to align the edges of a plurality of digital signals. For example, a delay lock loop circuit may be used to align the rising edge and/or the falling edge of a clock signal based upon a reference clock signal, to produce a synchronized clock signal. Many times, digital signals from multiple sources access one or more memory spaces in a memory, unit. It is desirable that these digital signals be synchronized for proper access of memory. Typical delay lock loops comprise a phase detect unit that detects the phase differences between a plurality of signals. The output of the phase detect unit is then used to affect the operation of a filter that adjusts the delay of an output of the delay lock loop.
The problems associated with the current methodologies of implementing the delay lock loop include an overreaction when performing delay compensation due to external factors on a digital line. These external factors that cause inadvertent adjustments of the delay lock loop include a noise spike on a bus or a control signal. These noise spikes may cause a delay lock loop circuit to be over-dynamic, wherein the delay lock loop circuit tracks a noise spike, thereby adding unintentional delays to the line.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
In one aspect of the instant invention, a device is provided to perform a filter control of a delay lock loop circuit. The device of the present invention includes a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop includes a filter to provide a filter response to the phase difference. The filter response is capable of providing a coarse delay and/or a fine delay.
In another aspect of the instant invention, a delay lock loop is provided to perform a delay function upon a signal. The delay lock loop of the present invention includes a forward path comprising an input path for receiving a reference signal and a delay path for providing at least one of a coarse delay and a fine delay upon the reference signal to provide an output signal. The delay lock loop of the present invention also includes: a feedback path to provide a feedback signal based upon the output signal; a phase detector to generate a shift signal based upon a phase comparison of the feedback signal and the reference signal; and a filter to receive the shift signal from the phase detector and provide at least one of a fine delay signal and a coarse delay signal for generating the output signal.
In another aspect of the instant invention, a circuit is provided to perform a filter control of a delay lock loop circuit. The circuit of the present invention comprises: a first delay unit to receive a reference signal and provide a delay upon the reference signal; a filter to apply a second delay upon the reference signal to generate an output signal; a feedback delay unit to provide a delay upon the output signal to generate a feedback signal; and a phase detector to determine a phase difference between the reference signal and the feedback signal and generate a shift signal.
In yet another aspect of the instant invention, a system board is provided for performing a filter control of a delay lock loop circuit. The system board of the present invention comprises a first device and a second device. The first device includes a memory location for storing data and a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop includes a filter to provide a filter response to the phase difference. The filter response includes providing at least one of a coarse delay and a fine delay. The second device is operatively coupled to the first device. The second device is adapted to access data from the first device based upon an operation performed by the delay lock loop.
In yet another of the instant invention, a memory device, which is capable of performing a filter control of a delay lock loop circuit, is provided. The memory device of the present invention includes delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop includes a filter to provide a filter response to the phase difference. The filter response includes providing at least one of a coarse delay and a fine delay.
In another aspect of the instant invention, a method is provided for performing a filter control of a delay lock loop circuit. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A synchronized output signal is generated based upon the coarse delay and the fine delay.
In yet another aspect of the present invention, a computer readable program storage device encoded with instructions is provided for performing delay function upon a signal. A computer readable program storage device encoded with instructions that, when executed by a computer, performs a method, which comprises: providing at least one of a coarse delay and a fine delay upon a reference signal based upon a phase shift between the reference signal and a feedback signal; and generating a synchronized output signal based upon the coarse delay and the fine delay.